Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be configured to provide user-defined features. PLDs typically include various components, such as programmable logic cells, memory cells, digital signal processing cells, input/output cells, and other components. The PLD components may be interconnected through signal paths provided by routing wires of the PLD to implement a desired circuit design.
However, PLDs typically have a limited supply of routing wires available to interconnect components from different portions of the PLD. This differs from conventional application-specific integrated circuits (ASICs) in which empty physical spaces may be reserved to implement additional signal paths at a later time if desired. Thus, if a given circuit design requires too many signals to be interconnected between certain regions of a PLD, the limited number of available signal paths may become nearly or completely exhausted, leading to congestion in the PLD signal paths. This can be especially problematic for PLDs with large cell sizes that may require correspondingly large numbers of interconnected signal paths. Therefore, the placement of components in a PLD (e.g., the position of various PLD components used to implement a circuit design) is an important PLD design consideration.
Unfortunately, existing approaches to determining PLD congestion are often unsatisfactory. For example, in one approach, rough approximations of routing resource requirements are used in order to save time and computing resources. However, the use of such approximations can result in considerably inaccurate routing resource calculations. In another approach, PLD congestion is frequently recalculated to improve the quality of results. Nevertheless, this alternative approach requires long computing times and significant computing resource commitments which can become cost-prohibitive and impractical for large PLD designs. Accordingly, there is a need for an improved approach to determining the placement of components in PLDs.